Any modern digital circuit system, especially some large digital processing systems, is often impossible to process all the data at once, so in the process of processing Some data and codes that need to be processed must be registered first, so that they can be accessed at any time when needed.
In the working process of the digital circuit system, the operation of temporarily storing the binary data or code being processed is called registering, and the circuit that realizes the registering function is called register. Register is one of the most basic sequential logic circuits. It is almost ubiquitous in various digital circuit systems and is widely used. Commonly used integrated circuit registers are named according to the number of bits that can store data, such as 4-bit registers, 8-bit registers, and 16-bit registers.
According to its functions, registers can be divided into two categories: digital registers and shift registers. If distinguished according to the different types of transistors used in the internal circuit of the register, it can be divided into many types such as transistor-transistor logic (TTL) and complementary field effect transistor logic (CMOS). At present, TTL registers and CMOS registers are the most used. They are all medium and small-scale integrated circuit devices.
The register circuit is the basic module of the digital logic circuit. Registers are used to store a set of binary codes, which are widely used in various digital systems and digital computers. Since one flip-flop can store one-bit binary code, N flip-flops can store N-bit binary code. For the flip-flops in the register, they only need to have the function of setting high level 1 and setting low level 0. Therefore, whether it is a trigger with a synchronous RS structure, or a trigger with a master-slave structure or an edge trigger structure All devices can form a register circuit.
In the computer CPU, in order to cooperate with the arithmetic operation of the full adder, N flip-flops can be connected in series to form a shift register. For example, a shift register with data shifting composed of four-bit D flip-flops and a shift waveform diagram are shown in Figure 1.
Basic register circuit
The basic register is composed of flip-flops, a flip-flop is a register, it can store a binary number. When it is necessary to store four-bit binary numbers, as long as four flip-flops are connected in parallel, a four-bit binary register can be formed, which can accept and store four-bit binary numbers. Figure 2 is a basic register logic circuit composed of 4 D flip-flops, the cP end of each flip-flop is connected in parallel as the control end. The number to be stored is added to the D input terminal of the trigger. The CP terminals of the four flip-flops are connected together to become the control terminal of the register, and the number to be stored is added to the D input terminal of the flip-flop.
According to the nature of D flip-flops, the above-mentioned registers have the following basic features.
When CP=0, the trigger keeps its original state, namely:.
When CP=1 (rising edge), the state of the flip-flop is the state of the D input terminal, namely:.
It can be seen that the D flip-flop will only receive and store numbers when CP=1 (rising edge).
In addition, because the terminals of the 4 flip-flops are also connected in parallel. Therefore, if a negative pulse is added to the watt D terminal, all the flip-flops can be set to the 0 state. This process is usually called clearing, also called setting the 0 terminal.
If you want to store the binary number 1001, they are added to the D input of the flip-flop respectively. When the clock pulse CP arrives, because the characteristic of the D flip-flop is when CP=1, so at the rising edge of the CP pulse, the state of the 4 flip-flops is set to 1001 from high to low, as long as there is no clearing Zero pulse or new received pulse and number, the register will always remain in this state, that is, the input binary code 1001 is stored in this register. If you want to take out the 1001 number from the register, you can get it from each Q output terminal of the register.
Move register circuit
The shift register circuit is the same as the latch circuit, both of which are temporarily storing data. Digital circuits often need to perform addition, subtraction, multiplication and division operations. Addition and subtraction operations are usually completed by adders and subtractors, while multiplication and division operations are completed by shifting and then adding and subtracting. When the digital signal is transmitted, the method of transmitting the digits one by one in sequence is called serial transmission, and the transmission of several digits at the same time is called parallel transmission. Therefore, in addition to requiring it to receive, store and transmit numbers, the register circuit is sometimes required to shift the numbers. This kind of register circuit is called a shift register circuit.
The shift register is an important part of the digital system and is widely used. For example, in serial operation, a shift register is needed to send binary data-bit by bit in sequence, and then a full adder is used to perform the operation. The result of the operation is stored in the shift register bit by bit. In some digital devices, it is necessary to convert the data transmitted in parallel to serial transmission, or to convert the data transmitted in serial to parallel transmission, and to complete these conversions, a shift register is also needed.
From the perspective of logical structure, the shift register circuit has the following two notable features.
(1) Composed of the same register unit
The shift register is composed of the same register unit. Generally speaking, the number of register units is the number of bits of the shift register. In order to complete different shift functions, the connection between the output of each register unit and the input of the next register unit adjacent to it is also different.
(2) Common clock
All register units share a clock. Under the action of the common clock, the work of each register unit is synchronized. Every time a clock pulse is input, the data of the 7 register will be sequentially shifted by one bit to the left or right. The register unit is generally a flip-flop of a master-slave structure.
Types of shift registers
CMOS shift registers are medium-scale integrated circuits, which can usually be classified according to different data transmission methods. From the perspective of data input methods, shift registers have The difference between serial input and parallel input. Serial input is to send the data to be input into the register bit by bit from an input terminal under the action of a clock pulse. Parallel input is to send the data to be input from several input terminals into the register at the same time.
In the CMOS shift register, some varieties have only one input method, for example, only have a serial input method, but some varieties have both parallel and serial two methods at the same time. The serial input data is added to the input terminal of the first register unit, and is input under the action of the clock pulse; the data transmission speed is slower. Parallel input data is generally sent in by the R and S ends of the register unit, and the transmission speed is faster.
Register circuit modeling
Registers and combinational logic are the two basic elements of digital logic circuits. Registers are generally associated with synchronous sequential logic, and their characteristic is that only when the edge of the clock (rising or falling edge) arrives, the output may change. According to different realization goals, the modeling structure of the register is slightly different, and the following points need to be paid attention to:
①Register signal declaration: The register definition is of reg type. But please note that the anti-proposition of this proposition is not necessarily true. Although some signals are defined as reg type, the final integrated realization result is not a register. For example, although "cnt-out-plus" is designated as reg type, it is pure combinational logic when it is implemented. This signal is a register only when it is defined as a reg type and the always sensitive table is posedge or negedge edge sensitive operation.
②Clock input: Process data on the positive or negative edge of each clock. The positive or negative edge of the data works, which is specified by posedge and negedge in the always sensitive table.
③Asynchronous reset/set: Most register models of target devices include asynchronous reset/set terminals. Asynchronous reset/set means that no matter whether the clock edge is valid or not, when the reset/set signal's valid edge arrives, the reset/set functions immediately. When specifying asynchronous reset/set, you only need to add the valid edge of the reset/set signal to the always sensitive table. The asynchronous reset circuit described in the following example is one of the most commonly used forms of register reset.
④Synchronous reset/set: any register can realize the synchronous reset/set function. When synchronous reset/set is specified, there is only clock edge signal in the sensitive table of always. When the synchronous reset/set signal changes, the synchronous reset/set does not happen immediately, only when the clock edge is taken to the synchronous reset/set When the effective level of the clock edge is reached, the reset/set operation will be performed at the time when the clock edge arrives.
⑤The problem of using the rising and falling edges of the clock at the same time: Sometimes due to data sampling or data phase adjustment requirements, the designer will use the posedge and negedge of the clock in an always sensitive table, or in both In an always sensitive table, the posedge and negedge of the clock are used to operate certain register circuits. Under these two descriptions, when the upper or lower edge of the clock arrives, the register circuit will do the corresponding operation. This double-edge circuit can often be equivalent to a single-edge operation circuit that uses a frequency-multiplied clock of the original clock. For the design implemented in PLD, it is often not recommended to use the upper and lower edges of the clock at the same time, because the embedded PLL/DLL and some clock circuits in the PLD can only guarantee very good indicators for one edge of the clock. The jitter, skew, slope and other indicators of the other edge may not be very optimized. Sometimes using the positive and negative edges of the clock at the same time will cause certain performance degradation due to clock jitter, skew, duty cycle, slope and other issues. Therefore, the recommended approach is to multiply the original clock by PLL/DLL, and then use the single edge (such as the rising edge) of the multiplied clock to operate. However, the circuit design cannot be generalized. If the two edges of the clock must be used to operate the same register, the designer should be clear that this is equivalent to using a frequency multiplier clock.