In fact, it is the "stamping" of higher-level interrupts. The processor is executing the interrupt, and it has accepted another more urgent "urgent", and turned to deal with it. A higher level of interruption behavior!
An interrupt source with a high priority can interrupt an interrupt service routine with a low priority, which forms a set of interrupt service routines. In the case of interrupt service routines, so-called interrupt nesting is formed.
The process in which the MCU suspends the current program and transfers to respond to the interrupt request is called interrupt response; in order to enable the system to respond to and process all interrupts in a timely manner, the hardware The interrupt source is divided into several levels, called interrupt priority.
There are two priority levels for interrupts: query priority and execution priority.
The query priority is the default in the datasheet or book (IP register is not set, 00H after power-on reset) priority:
External Interrupt 0> Timer/Counter 0 > external interrupt 1 > timer/counter 1 > serial interrupt
or int0, timer0, int1, timer1, serial port or INT0, T0, INT1, T1, UART
In fact, they are all query priority levels. First, the query priority cannot be changed or set. This is an interrupt priority queuing problem, which refers to the order in which the interrupt arbiter selects which interrupt source is processed first when multiple interrupt sources generate interrupt signals at the same time. This has nothing to do with whether the nesting of interrupt service routines occurs. When the CPU queries each interrupt flag bit, it will query in sequence according to the above five query priority order. When several interrupts are requested at the same time, it will first query the interrupt flag bit with the highest priority query priority, but it does not mean high The interrupt service of the inquiry priority can interrupt the interrupt service of the low inquiry priority that has been and is being executed.
For example: when counter 0 interrupt and external interrupt 1 (according to query priority, counter 0 interrupt>external interrupt 1) arrive at the same time, it will enter the interrupt service function of timer 0; but in external interrupt When the interrupt service function of 1 is servicing, any interrupt can't interrupt it at this time, including the external interrupt 0 with a higher logic priority than the counter 0 interrupt.
The execution priority of the interrupt is your setting of the IP register. In the case of 2 priority levels, if a bit is 1, the corresponding interrupt source is high priority; if it is 0, it is low priority.
There are three principles regarding the priority of interrupts:
1. When the CPU receives several interrupts at the same time, it first responds to the interrupt request with the highest priority;
2. The ongoing interrupt process cannot be interrupted by a new interrupt request of the same level or low priority;
3, the ongoing low priority interrupt service can be interrupted by a high priority interrupt request;
If there is more than one interrupt request in the same execution priority, there is an interrupt priority queuing problem. The queue of interrupts with the same execution priority is formed by the natural priority determined by the hardware of the interrupt system. The order of priority from high to low is:
External Interrupt 0> Timing/Counting 0> External Interrupt 1> Timing /Count 1>Serial interface
For example: set IP=0x10, that is, set the serial port interrupt to the highest priority, then the serial port interrupt can interrupt any other interrupt service function to achieve nesting, and only the serial port interrupt Can interrupt other interrupted service functions. If the serial port interrupt is not triggered, the logic priority is still maintained among the other interrupts, and they cannot be nested with each other.
About interrupt nesting. It can be said that when an interrupt is being executed, if the interrupt priority register IP is set in advance, then when a higher priority interrupt comes, interrupt nesting will occur, and if it is not set, no nesting will occur. ; If there is an interrupt trigger of the same priority, it is not in "continuous application", but its corresponding interrupt flag position is a certain position in the IE register. When the CPU finishes executing the current interrupt, it will follow the query priority Re-check each interrupt flag bit and enter the corresponding interrupt.
Remember, when the IP is not set, the MCU will queue up to enter the service according to the query priority (or logic priority). If you want a priority response to an interrupt, you must set the IP and change the execution priority (or physical priority). It should be noted that when IP (Interrupt priority is interrupt priority, the same below) is set, when a low execution priority interrupt is running, if an interrupt with a high execution priority is generated, the nested call will enter the high execution Priority interrupts. If you are a program written in C language and use the register group during interrupt service, please note that two interrupt service routines with different priorities should not use the same group of registers.
1 When each interrupt is of low priority, if the overflow of timer 0 enters the interrupt. In the process of interrupt processing, external interrupt 0 is also triggered, so will interrupt nesting occur?
Answer 1: In the case that the IP has set the priority of external interrupt 0 in advance, the CPU will suspend the interrupt service of timer 0, enter the external interrupt 0 service routine, and return to the timer after execution 0 interrupt service routine. Otherwise it won't.
2 If Timer 0 is interrupted, it enters the interrupt processing routine. At this time, the external interrupt 1 condition trigger condition is met. Because the natural priority of timer 0 is higher than that of external interrupt 1, the interrupt handler of timer 0 continues to execute. Assume that the external interrupt 1 is triggered during the execution of the timer interrupt handler. If the condition disappears, after the timer 0 interrupt is processed, will the program still enter the external interrupt 1 processing routine?
Answer 2: It will definitely enter the interrupt; after the trigger condition of external interrupt 1 is met, the interrupt flag of external 1 will be set. Even if the trigger condition of external interrupt 1 disappears later, it will not be cleared. Bit interrupt flag, so after the interrupt processing of timer 0 is completed, the program will still enter the external interrupt 1 handler after judging that the interrupt flag of the external interrupt is 1. The hardware will only be executed when the reti instruction is executed in the external interrupt 1 handler. Clear the interrupt flag of external interrupt 1 (this is why the interrupt return uses the reti instruction and cannot be replaced with ret)...
Interrupt processing is divided into Four stages:
1. Save the scene of the interrupted program, the purpose is to return to the original interrupted place to continue execution after the interrupt is processed;
2 Analyze the source of the interrupt, determine the cause of the interrupt, and consider the priority of the interrupt when multiple interrupts are requested at the same time;
3, go to execute the corresponding processing program;
4. Restore the scene of the interrupted program and continue to execute the interrupted program.
Clear the interrupt flag
There are two ways for MCU to clear the interrupt flag
One is to write "in the register of the interrupt flag through software code" 1" to complete the clearing operation of the flag bit
The second type is when the MCU responds to the interrupt and executes the interrupt service program (that is, the pointer of the program counter jumps to the interrupt service program code area). The hardware automatically performs the reset operation.
Features of multi-level interrupts
1. If a system has n-level interrupts, there are n interrupt request triggers in the MCU, which are collectively called interrupt request registers; the corresponding There are n interrupt mask flip-flops, collectively called interrupt mask registers. Different from single-level interrupts, in multi-level interrupts, the content of the interrupt mask register is a very important program scene. Therefore, when responding to interrupts, it is necessary to save the contents of the interrupt mask register and set a new interrupt mask state. Generally, after a certain level of interrupt is responded, it is necessary to set "1" (close) the interrupt mask trigger of this level and the priority lower than this level, and set "0" (open) the higher-level interrupt mask trigger. To achieve normal interrupt nesting.
2. Each level of the multi-level interrupt can have only one interrupt source or multiple interrupt sources. Interrupt nesting can be achieved between multi-level interrupts, but interrupts with different interrupt sources in the same level cannot be nested. It must be processed after one interrupt is processed, and then respond to and process other interrupt sources in the same level.