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Interrupt instruction

Special function instructions

3.9 S7-200 special function instructions

1. Interrupt instruction

The PLC CPU is in the entire control process Some controls depend on external events. For example, only when the external device requests the CPU to send data, the CPU can send data to the device. The execution of this kind of control depends on the request of the external device and the response of the CPU. When the CPU accepts the request of the external device, the CPU will suspend its current work to complete the request of the external process. , This working method is called interrupt mode.

Before starting the interrupt program, the interrupt event must be connected with the program segment that you want to execute when this event occurs. Let

Use the interrupt connection command (ATCH) to establish the connection between the interrupt event (specified by the interrupt event number) and the program segment (specified by the interrupt program number)

. When the interrupt event is connected to the interrupt program, the interrupt is automatically started.

Using the interrupt separation instruction (DTCH) can delete the connection between the interrupt event and the interrupt program, thus closing a single interrupt

event. The interrupt separation instruction returns the interrupt to an inactive or ignored state.

S7-200 can trigger a total of 34 interrupt events in 5 categories. Among them, there are 8 interrupt events caused by input signals,

There are 6 interrupt events caused by communication ports, 4 interrupt events caused by timers, and interrupt events caused by high-speed counters.

14 items, there are 2 interrupt events caused by pulse output instructions. As shown in the table

S7-200 can right-click any position in the ladder diagram editor and choose to insert interrupt. For S7-200, you can also right-click the block icon from the

instruction tree and select Insert Interrupt from the pop-up menu. S7-200 can also insert interrupt from the program editor window, right-click from the menu. Once a new interrupt is created, a new tab will appear at the bottom of the program editor,

representing the new interrupt program.

(1)Interrupt connection instruction

·The indication of the interrupt connection instruction: the interrupt connection instruction is composed of the enable end of the instruction EN, the instruction mnemonic

ATCH, The interrupt program number (entry number) INT n and the event number EVNT of the interrupt event are composed. Use ladder

to show as shown in Figure 3-9-1.

·The operation of the interrupt connection instruction: the interrupt connection instruction (ATCH) makes the interrupt event (EVNT) and the interrupt program number (INT) related, and initiates the interrupt event. According to the designated event priority group, the PLC provides services to interrupts in the order of first-come, first-served.

Only one user interrupt can be activated at any time. When other interrupts are active, the CPU issues an interrupt to temporarily enqueue the queue and wait for later processing. If too many interrupts occur and the queue cannot be processed, set the queue overflow status bit. When the team is empty, reset these bits.

Data range

INT; 0~127

EVENT: 0~33

(2) Interrupt separation instruction

· Representation of the interrupt separation instruction: The interrupt separation instruction is composed of the enable terminal EN of the instruction, the instruction mnemonic DTCH

and the event number EVNT of the interrupt event. Use ladder diagram or statement list as shown in Figure 3-9-2. ·The operation of the interrupt separation instruction: the interrupt separation instruction (DTCH) cancels the connection between the interrupt event (EVNT) and all interrupt programs, and closes the interrupt event. Data range:

< p>EVENT: 0~33

(3)Interrupt return instruction

·The expression of the interrupt return instruction: the interrupt return instruction is represented by the instruction mnemonic RETI

Constitute. Use ladder diagram or statement list as shown in Figure 3-9-3.

·The operation of the interrupt return instruction: the interrupt return instruction (RETI condition return) can be used to return from the interrupt according to the previous logic condition.


Micro/WIN 32 automatically adds unconditional returns for each interrupt program. When writing a program, the user does not need to write an unconditional return instruction. Interrupt handling provides a response to special internal or external interrupt events.

When writing the interrupt service program, make the interrupt program short and simple, speed up the execution speed

and don't delay too long. Otherwise, unexpected conditions may cause abnormal operation of the equipment controlled by the main program. For interrupt service routines, the saying goes, "The shorter the better," this is absolutely correct.

The DISI, ENI, HDEF, LSCR, END instructions cannot be used in the interrupt program.

(4) Interrupt enable instruction

·The representation of interrupt enable instruction: interrupt enable instruction is composed of

instruction mnemonic ENI. Use ladder diagram or statement list

to show as shown in Figure 3-9-4. · The operation of the interrupt enable instruction: the interrupt enable instruction

(ENI) instruction globally starts all interrupt events. Once the

enter the run mode, each interrupt event that has been activated

is allowed to be executed.

(5) Interrupt prohibition instruction

·The expression of interrupt prohibition instruction: Interrupt prohibition instruction is composed of

instruction mnemonic DISI. Use ladder diagram or statement list as shown in Figure 3-9-4.

·The operation of the interrupt prohibition instruction: the interrupt prohibition instruction (DISI) can globally close all interrupt events. Interrupt prohibition means

The order allows the interrupt to enter the queue, but does not allow the interrupt program to be started.

(6)Several issues further explained in the interruption

1) About calling a subroutine in an interruption: A nested subroutine can be called from an interruption program. The accumulator and logic stack

are shared in the interrupt routine and the called subroutine.

2) About sharing data: Data can be shared between the main program and one or more interrupt programs. For example, a certain place in the user's main program can provide data to be used for a certain interrupt program, and vice versa. If the user program shares data, you must consider

the impact of the asynchronous nature of interrupt events, because interrupt events will appear anywhere the user's main program is executed. Sharing

The solution to the problem of data consistency depends on the operation of the interrupt program when the main program is interrupted by an interrupt event.

There are several programming techniques that can ensure the correct sharing of data between the user's main program and the interrupt program. These techniques

or restrict the access method of the shared memory unit, or make the instruction sequence using the shared memory unit not be interrupted.

The statement list program shares a single variable. If the shared data is a single byte, word, or double word variable, and the user program is written in

STL, then the intermediate value obtained by operating the shared data is only stored in the non-shared memory unit or accumulator In, you can ensure correct shared access.

Ladder diagram programs share a single variable. If the shared data is a single byte, word or double word variable, and the user program is written with

ladder diagram, then the shared memory unit can be accessed by using only the Move instruction (MOVB, MOVW, MOVD, MOVR),< /p>

can ensure correct shared access. These Move instructions are not affected by interrupt events when they are executed.

The statement list or ladder diagram program shares multiple variables. If the shared data consists of some related bytes, words or double words,

then you can use the interrupt prohibit/allow instruction ( DISI and ENI) to control the execution of the interrupt program. At the beginning of the user program

Interrupts are prohibited at the place where the shared memory unit is operated. Once all operations affecting the shared memory unit are completed, allow the interrupt

, but this method will cause Delay in response to interrupt events.

3) About communication port interruption:

The serial communication port of PLC can be controlled by ladder diagram or statement list program. This mode of operation of the communication port is called the free end

port mode. In the free port mode, users can program to define the baud rate, the number of bits per character, parity and communication protocol

protocol. The use of receiving and sending interrupts can simplify the program's control of communication.

4) About I/O interrupts:

I/O interrupts include rising or falling edge interrupts, high-speed counter interrupts and pulse train output (PTO) interrupts. S7

-200 CPU can use the rising or falling edge of input I0.0 to I0.3 to generate interrupts. Rising edge events and falling edge events can be captured by these input points. These rising or falling edge events can be used to indicate conditions that must be paid attention to when an event occurs


The high-speed counter interrupt allows interrupts to be generated in response to events such as the current value equals the preset value, the counter counting direction change, and the counter external reset

bit. Each high-speed counter can respond to high-speed events in real time, and the PLC scan rate cannot control these high-speed events. The pulse train output interrupt gives an indication that the specified number of pulses has been output. A typical application of pulse train output is stepper motor. You can allow each of the above-mentioned interrupts by connecting an interrupt program to the corresponding I/O event.

5) About time base interrupts:

Time base interrupts include timer interrupts and timer T32/T96 interrupts. The CPU can support timer interrupts. You can use timed

interrupts to specify a periodic activity. The period is in increments of 1ms, and the period can be from 5ms to 255ms. For timing interrupt 0, write the cycle time into SMB34; for timing interrupt 1, write the cycle time into SMB35. Whenever the timer overflows,

The timing interrupt event transfers the control right to the corresponding interrupt program. Usually timed interrupt can be used to control the sampling of analog input or execute a PID loop at fixed time intervals.

When an interrupt program is connected to a timed interrupt event, if the timed interrupt is allowed, then the timing will start.

During the connection, the system captures the cycle time value, so subsequent changes will not affect the cycle. To change the cycle time, first

must modify the cycle time value, and then reconnect the interrupt program to the timing interrupt event. When reconnecting, the timer interruption function clears any accumulated value during the previous connection and restarts the timer with the new value.

Once enabled, the timer interrupt will run continuously, and the connected interrupt program will be executed every time the specified time interval overflows.

If you exit the RUN mode or separate the timer interrupt, the timer interrupt is prohibited. If the global interrupt prohibition instruction is executed, the interrupt event will continue to appear at certain

, and each timed interrupt event that appears will enter the interrupt queue and wait until the interrupt is allowed or the queue is full.


The timer T32/T96 interrupt allows timely response to a given time interval. These interrupts only support lms resolution

delay on timer (TON) and delay off timer (TOF) T32 and T96. T32 and T96 timers work normally in other ways.

Once the interrupt is allowed, when the current value of the effective timer is equal to the preset value, the connected interrupt program is executed in the normal lms timing of the CPU refresh. First connect an interrupt program to the T32/T96 interrupt event, and then allow

to allow the interrupt.

6) About interrupt priority and queuing:

Interrupts are executed in the following fixed priority order. Communication (highest priority), I/O interrupt, time base interrupt (lowest

priority). Within each designated priority level, the CPU processes interrupts on a first-come, first-served basis. At any point in time, only one

user interrupt program is executing. Once the interrupt program starts to execute, it has to be executed to the end. And it will not be interrupted by other

interrupt programs, or even higher priority interrupt programs. When another interrupt is being processed, the new interrupt

needs to be queued for processing.

Sometimes, there may be more interrupts than the queue can hold. Therefore, the queue overflow memory maintained by the system

bit indicates the type of interrupt event that is missing. Use these queue overflow memory bits only in the interrupt program, because these bits will be reset when the queue becomes empty or control returns to the main program.

7) Restrictions on using interrupts:

A program can have up to 128 interrupts. Within their respective priority ranges, PLC uses the principle of first-come, first-served

to handle interrupts. At any time, only one user interrupt program can be executed. Once an interrupt program starts to execute, it will execute until completion. It cannot be interrupted by another interrupt program, even if the priority of another program is higher. When the interrupt is being processed

A new interrupt that occurs needs to be queued for processing.

The DISI, ENI, HDEF, LSCR and END instructions cannot be used in the interrupt program.

(7) Interrupt program programming steps

·Establish interrupt program INT n (same method as creating subroutine)

·Write in interrupt program INT n Its application program

·Write interrupt connection instruction (ATCH)

·Enable interrupt (ENI)

·If necessary, you can write interrupt disconnect instruction (DTCH) ) Example 3-9-1: Figure 3-9-5 is a programming example of using a timer interrupt to read an analog quantity.

The main program OB1 has a statement whose function is to scan the first time after the PLC is powered on

(SMO.l=1), call the subroutine SBRO, and initialize it.

The function of the subroutine SBR0 is to set the timer interrupt. Among them, suppose

The time interval of fixed timer interrupt 0 is l00ms. The transfer instruction MOV stores

100 in SMB34, which is to set the time interval of the timer interrupt 0.

The interrupt connection command ATCH connects the timing interrupt 0 (interrupt event number

is 10) and interrupt program 0 (interrupt entry is INT0),

And allow interruption of the event. The last sentence of the subroutine is the global enable

interrupt (ENI). Only with this one, the interrupt event that has been allowed to interrupt can be actually executed.

The function of the interrupt service routine INT0 is to execute the operation of reading the analog AIW0 once every time it is interrupted, and transfer this value to


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